Three-dimensional time-of-flight (TOF) systems that provide a measure of distance (Z) from the system to a target object without depending upon luminosity or brightness information obtained from the target object are known in the art. Many exemplary type TOF systems are described in numerous U.S. patents obtained by Canesta, Inc., which patents are now assigned to Microsoft, Inc. For example U.S. Pat. No. 6,323,942 entitled CMOS-Compatible Three-Dimensional Image Sensor IC (2001) describes TOF systems that emit optical energy and determine how long it takes until at least some of that energy reflected by a target object arrives back at the system to be detected. Emitted optical energy traversing to more distant surface regions of a target object before being reflected back toward the system will define a greater TOF than if the target object were closer to the system. If the roundtrip TOF time is denoted t1, then the distance between target object and the TOF system is Z1, where Z1=t1·C/2, where C is velocity of light. Such systems can acquire both luminosity data (signal amplitude) and TOF distance, and can realize three-dimensional images of a target object in real time.
A more sophisticated TOF system is exemplified by U.S. Pat. Nos. 6,515,740 (2003) and 6,580,496 (2003) respectively Methods and Systems for CMOS-Compatible Three-Dimensional Imaging Sensing Using Quantum Efficiency Modulation, obtained by Canesta, Inc. FIG. 1A depicts an exemplary phase-shift detection system 100 according to the '740 or the '496 patents. System 100 determines TOF by examining relative phase shift between transmitted light signals and signals reflected from the target object. Detection of the reflected light signals over multiple locations in the system pixel array results in measurement signals that are referred to as depth images.
Referring to FIG. 1A, TOF system 100 includes a two-dimensional array 130 of optical detectors 140, each of which preferably has dedicated circuitry 150 for processing detection charge output by the associated detector. By way of example, array 130 might include 100×100 pixels 140, and thus include 100×100 processing circuits 150. IC 110 also includes a microprocessor or microcontroller unit 160, memory 170 (which preferably includes random access memory or RAM and read-only memory or ROM), a high speed distributable clock and timing system 180, and various computing and input/output (I/O) circuitry 190. Clock system 180 preferably provides two preferably complementary clock signals per pixel detector. Quantum efficiency modulation performs a mixing function that demodulates phase (i.e., delay) information in the detected incoming optical energy. Among other functions, controller unit 160 may perform distance to object and object velocity calculations.
Under control of microprocessor 160, appropriately controlled drive waveforms are output by a low power generator 115, (e.g., perhaps 50 mW peak), which waveforms control a source of optical energy 120. Optical energy source 120 is thus preferably periodically energized and emits optical energy via lens 125 toward an object target 20 a distance Z away. The optical energy emitted by source 120 will have emissions of known frequency (perhaps 50 MHz to a few hundred MHz) for a time period known as the shutter time (perhaps 10 ms). Typically the optical energy is light emitted perhaps by a laser diode or LED device 120, and is denoted in FIG. 1A as S1=cos(ω·t) although the emitted waveform need not be a perfect cosine. Some of the S1 emitted optical energy will be reflected off the surface of target object 20 back toward TOF system 100, and is denoted as S2=A·cos(ω·t+φ), where A is an amplitude coefficient and φ is phase shift. This reflected optical energy S2 passes through an aperture field stop and lens, collectively 125, and falls upon two-dimensional array 130 of pixel (optical energy) detectors 140 where an image is formed.
Note that S1 optical energy from emitter 120 and detected S2 active optical energy signals within pixel detectors 140 are synchronous to each other such that phase difference φ and thus depth distance Z can be measured for each pixel detector. FIG. 1B depicts an exemplary idealized emitted S1 signal, whereas the phase-delayed signal of FIG. 1B is an exemplary idealized return signal S2 that will be detected by TOF system 100 and processed to yield information, include distance Z to target object 20.
In some implementations, each imaging pixel detector 140 captures time-of-flight (TOF) required for optical energy transmitted by emitter 120 to reach target object 20 and be reflected back for detection by two-dimensional sensor array 130. The optical detectors in array 130 can operate synchronously relative to active optical energy from emitter unit 120. If desired, such synchronous detection operation may be implemented with an electronic high speed shutter mechanism perhaps associated with lens 125. Using this TOF information, distances Z can be determined. Advantageously system 100 can be implemented on a single IC 110, without moving parts and with relatively few off-chip components. Note that while only active optical energy is emitted from unit 120, incoming optical energy may include both ambient optical energy components, sunlight perhaps, as well as the desired target object reflected-back active optical energy components.
As described in the '740 and '496 patents, optical energy detected by array 130 will include amplitude or intensity information, denoted as “A”, as well as phase shift information, denoted as φ. As shown by FIGS. 1B and 1C, the phase shift information varies with distance Z and can be processed to yield Z depth data. For each pulse or burst of optical energy transmitted by emitter 120, a three-dimensional image of the visible portion of target object 20 is acquired, from which intensity and Z data is obtained, denoted DATA. TOF systems according to the '740 and '496 patents obtain depth information Z by acquiring at least two samples of the target object (or scene) 20 with 90° phase shift between emitted optical energy and the pixel detected signals. While two samples is a minimum figures, preferably four samples, 90° apart in phase, are acquired to permit detection error reduction due to mismatches in pixel detector performance, mismatches in associated electronic implementations, and other errors. On a per pixel detector basis, the measured four sample data are combined to produce actual Z depth information data.
Understandably, the accuracy of Z distance measurements can be affected by the accuracy of the clock timing signals coupled to exciter 115, and to the control of phase and/or shape of the signals output by emitter 120. Accurate Z measurements require that the phase of the signal output by emitter 120 be both stable and known relative to the phase (or any of the multiple phases) associated with time measuring unit 180 of system 100, otherwise, time measurement accuracy is degraded.
U.S. Pat. No. 7,636,150 issued to Canesta, Inc., entitled “Method and System to Enhance Timing Accuracy for Time-of-Flight Systems” describes many of the challenges associated with implementing timing systems in TOF systems. Other exemplary TOF systems are described in U.S. Pat. Nos. 6,323,942, 6,515,740, and 7,405,812, which patents were issued to Canesta, Inc. and are now assigned to Microsoft, Inc. Applicants refer to and incorporate by reference all of the patents cited herein for background reference purposes.
In many applications it is desired to operate TOF systems using battery power, yet TOF clock driver circuitry can often consume substantial operating power. For example, TOF systems exemplified by the '740 and '496 patents employ an array of CMOS image sensor elements that are driven by two preferably complementary clocks, which preferably form part of clock unit 180 in FIG. 1. A clock driver outputs the two clock signals, which alternately steer detection photocurrent to different pixel outputs and enable measurement of the received image phase or delay. Each pixel in the array presents a load to the clock driver output, and as a result the total cumulative capacitive load on the clock driver can be quite large. A high clock rate is preferred to increase phase differences produced by distances to the target object. However the combination of large capacitive clock load and high clock switching rate leads to high power dissipation due to C·V2·f losses, where C is effective capacitive load, V is operating potential, and f is clock frequency. If the two clock signals were allowed to have arbitrary phase relationships, the power dissipation would effectively double, and become 2·C·V2·f.
Clock circuits including TOF clock circuits frequently are implemented using CMOS buffers and inverters. It is useful to briefly review prior art CMOS inverters with reference to FIGS. 2A-2C. FIG. 2A shows a conventional CMOS inverter comprising a series-connected PMOS-NMOS transistor pair coupled between two power supplies, denoted V1, V2, where V1>V2, and commonly V2 may be ground. Typically the input gate notes (G) are coupled together, as are the output drain nodes (D). The source nodes (S) are coupled to the respective power supplies.
Referring to FIGS. 2A and 2B, when the input voltage signal (drawn with solid line) is low, ideally 0 VDC, the PMOS transistor will be biased ON, and the NMOS transistor will be biased OFF. The result is that the output voltage signal (drawn in phantom line for ease of illustration) will be high, i.e., the inverted state from the low input signal. Conversely when the input voltage signal is high, ideally V1, the PMOS transistor is biased OFF, and the NMOS transistor is biased ON. The result now is that the output voltage signal will be low, i.e., the inverted state from the high input signal.
But in practice, during state transitions from low-to-high or high-to-low, both the PMOS and NMOS transistors may be simultaneously ON while the input signal transitions through a voltage regime intermediate logic “low” and logic “high” levels. During this interval, noted in FIG. 2B at tSC, the PMOS and NMOS transistors essentially define a short circuit (but for drain-source impedances) between the two power supplies. Thus, during this interval, denoted tSC, a relatively high short circuit current iSC is drawn from the V1 power supply, and passes through the transistors to the V2 power supply. Referring to FIG. 2C, assuming the CMOS inverter has symmetrical rise and fall transitions, the current spike during iSC may be depicted as having a triangular shape. Under these assumptions, the energy (E) consumed per switching period may be calculated as:E(energy)=0.5·(V1−V2)·iPEAK·tSC 
Understandably it is desired to minimize E, which goal can be achieved for a given power supply regime, i.e., V1, V2, by minimizing iPEAK and/or tSC. During time tSC some energy is wasted in each switching transient because useful electrical current flows from power supply V1 to V2, rather than flowing into the load connected to the CMOS inverter output. Clock drivers typically utilize inverter stages. Thus, an enhanced inverter design can contribute to clock drivers that dissipate less energy, and thus operate more efficiently.
What is needed is a clock driver architecture, suitable for use in clocking detector arrays in a TOF system. Such improved clock drivers should minimize power consumption, preferably by substantially reducing so-called short-circuit current in inverters used to implement the clock driver. Further, such clock driver architecture should preferably provide a mechanism to equalize charge present on the capacitive load seen by the clock driver output signals, to substantially further reduce power dissipation.
In other aspects, TOF system efficiency can also be enhanced by better utilizing incoming S2 optical energy. In some applications, TOF system performance requires higher power optical energy source(s). Finally, TOF system performance can be enhanced using advanced filtering concepts.
Embodiments of the present invention provide such an enhanced clock driver, and other enhancements for TOF systems and other systems.